1. Technical Field
The invention relates generally to programmable fuse circuitry, and more particularly, to programming fuses electronically and verifying the states of such programmed fuses, via a shift-register.
2. Related Art
Fuses and antifuses (collectively anti/fuses) are often used to permanently store binary data on an IC. Binary logic states are represented by the binary conductive state of the anti/fuse, being either xe2x80x9cONxe2x80x9d (i.e., conducting) and xe2x80x9cOFFxe2x80x9d (i.e., nonconducting). The related art depicted in FIG. 1 provides a plurality of (i.e. bank of) series connected circuit elements (e.g. circuit element 18) that each include a Master-Slave type shift-register (e.g. Digital Flip-Flop, DFF), to read-out the state of multiple on-chip fuses (e.g., 12a) after programming (e.g., by laser-blow) has been performed. These circuits 18 allow the actual state of programmable fuses circuits to be loaded from fuse latches (e.g., 42) in parallel into the bank of Master-Slave shift-registers (DFF) and then to be shifted serially to the output 36 of the shift-register bank where the state of the programable fuses can be read out.
The related art depicted in FIG. 1 provides a three-latch design comprising a fuse latch 42, a shift register master latch 44, and a shift register slave latch 46. The circuit 18 of related art provides the functionality of being able to verify the laser-programming state of fuses 12a that have each been incorporated within a voltage-divider network comprised of a load device (14a) and a fuse (12a ) connected in series between the supply voltage and ground. The state of each fuse is observed by (e.g., read into) the fuse latch 42 via a fuse output line 32 at the connection between the fuse 12a and the load device 14a. 
A data pattern can be serially scanned through the Shift Register 16 of a first stage out to a second Shift Register 16 of a second stage. This is achieved by sequentially activating the CK gate 64a and the CKN gate 66a with the signal CK and the signal CKN, respectively. This is an example of a conventional master-slave latch configuration. The data moves from master to slave in a first stage, from master to slave in a second stage, and so on to subsequent stages.
The related art circuit 18 of FIG. 1 is able to observe, but not to change the conductive state of the fuse 12a, and therefore requires that the final programming of the metal wire fuse 12a be performed externally (e.g., by laser fuse-blow at a laser programming station). The related art circuit 18 also draws current (i.e., consumes energy) through a non-blown metal wire fuse element 12a whenever the power supply voltage VDD is applied to the circuit, thus unnecessarily consuming power.
The present invention overcomes the limitations and deficiencies of the related art described above. The inventive circuit can perform final non-volatile programming of 2-state elements (e.g. fuses, anti-fuses, and electromechanical switches) via a serial shrift-register, obviating laser programming. An additional feature of the present invention is that it can verify the programming of a programmable anti/fuse circuit containing a plurality of anti/fuse elements (by serially scanning out the programmed anti/fuse values). A fuse latch is coupled to the two-state element (e.g., antifuse element) to determine whether it is in a conducting (i.e., low resistance) mode or non-conducting (i.e., high resistance) mode, corresponding to respective xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d conditions, by pulling-down a latch input node voltage when xe2x80x9cON.xe2x80x9d
Embodiments of the present invention provide a fuse programming and verification circuit that can program capacitative antifuses, conductive wire fuses (and other 2-state elements) and then verify and serially read out the actual state of such elements after programming. The inventive circuits provide the functionality of being able to verify the programming of the anti/fuse elements by sensing the conductive states of all the anti/fuse elements after selected elements have been programmed and scanning out that conductive state information as binary data. Additionally, the inventive circuits provide the functionality of being able to test any non-memory circuitry that depends on the memory being fully functional and operational while still at the wafer tester before having to xe2x80x9cblowxe2x80x9d (i.e., program) any fuses.
In a first embodiment, the foregoing functionality is achieved by a fuse programming and verification circuit implemented in a three-latch design comprising a fuse latch, a shift register master latch, and a shift register slave latch. In a second embodiment, the foregoing functionality is achieved by a fuse programming and verification circuit implemented in a two-latch design comprising an integrated fuse-master shift register latch, and a shift register slave (hold) latch. In alternative embodiments of the invention, the fuse element may be implemented by any two-state device, such as an anti-fuse or even a micro-, nano- or pico-electro-mechanical switch.
Accordingly, a first aspect of the invention provides a device for programming and verifying a non-volatile two-state element, including: a two-state element having a binary conductive state; and a latch operatively coupled to the two-state element being adapted to sense the conductive state of the two-state element, and being further adapted to store a binary bit representing the conductive state; and a logic gate operatively coupled to the two-state element for changing the conductive state of the two-state element according to a binary bit of programing data.
A second aspect of the invention provides method for programming and verifying a plurality of two-state elements, the method including scanning in programming data, then changing the conductive state of each two-state element of a subset of the plurality of two-state elements according to the programing data, and sensing and storing the conductive states of all the two-state elements as binary verification data and then scanning out the verification data.
The foregoing and other features of the invention will be apparent from the following detailed description of embodiments of the invention, as illustrated in the accompanying drawings.